The invention broadly relates to an electronic multi-level non-volatile memory device which is monolithically integrated in a semiconductor and incorporates a circuit structure for programming data contained in the memory.
In particular, the invention relates to a circuit structure for writing reference cells of a multi-level non-volatile memory, and the following description is made with reference to this field of application for convenience of explanation.
As it is well known in this specific technical field, recent developments in the manufacture of non-volatile memories, specifically memories of the EPROM, EEPROM and FLASH types, point toward an increase of their storage capacity by the adoption of multi-level architectures, that is, memory matrices whose cells can store multiple logic states.
A preliminary comparative review of the circuit structures with conventional two-level memories may help, however, to make the aspects of this invention more clearly understood.
Electronic memory devices usually comprise at least one matrix of memory cells laid into rows and columns of the matrix. Logic information can be written or read into/from each cell by suitably biasing the corresponding row or column.
A typical memory cell comprises a field-effect transistor having a control gate terminal, a floating gate region, a source terminal, and a drain terminal. A range of electric potentials separates the two possible logic states of a two-level memory cellxe2x80x94e.g., a logic xe2x80x9c0xe2x80x9d to indicate a programmed cell, and a logic xe2x80x9c1xe2x80x9d to indicate an erased cell.
In operation, for the purpose of discriminating the informational contents of a two-level non-volatile memory cell, the memory cell is compared with a structurally identical reference cell which contains a known logic value.
The operation for selecting a cell in order to read its informational contents consists of applying a suitable bias voltage to the control gate terminal of the memory cell. If the cell has previously been programmed, then an electric charge is trapped within its floating gate region, and the threshold voltage of the cell is such that makes the drain current conduction lower than the reference cell.
On the other hand, if the cell has been erased, no electric charge is trapped within its floating gate region, and the conduction state of the cell can be identified using an unbalanced-load technique of comparison with the reference cell.
Thus, a method most frequently used for reading from a flash type of memory cell consists of comparing the current drawn by the cell to be read and the current drawn by the reference cell. A simple comparator, known as sense amplifier, is used to perform the comparison and outputs a corresponding result.
In the instance of a multi-level memory device, no less than 2nxe2x88x921 references are needed to discriminate a cell having an n-bit storage capacity; such references may be voltage- or current-oriented, depending on the reading method applied.
As an example, a prior method of determining the state of an n-level memory cell is described in the U.S. Pat. No. 5,774,395, wherein the reference cell is electrically erased in order to determine the threshold voltage of the reference cell with high accuracy within a wide range of voltages, e.g., of xe2x88x925 to 15 Volts. Briefly, selected elements of the multi-level reference cell are electrically erased and re-programmed to allow a detection and a fine tuning of the multiple logic states present in a memory cell, i.e., disallow overlap of cell states.
Thus, unlike a two-level memory, the reference cells of a multi-level memory require an additional program circuitry for writing into the reference cells the intermediate logic levels to compare with the programmed or programmable ones in the memory cell matrix.
The prior art conventionally used in two-level non-volatile memories provides for allocation of the reference cells and of memory cells to the same matrix. However, this solution is not easily extended to multi-level memories because this would require a circuit area increase with the number of bits, and because the reference cells of a multi-level memory must be programmed.
These difficulties are emphasized by the use of different reference cells for reading and programming. In fact, a reference line including the same number of reference cells as the matrix cells could affect the reference cell read and/or program time quite significantly.
An embodiment of this invention provides a circuit structure whereby reference cells, preferably but not exclusively of the multi-level type, can be simply and accurately programmed with only a minor impact on the circuit area of the memory device and the programming speed of such reference cells.
The circuit structure includes, for each matrix block included in a specific read sector, a corresponding external array which contains all the reference cells needed for comparison with the selected matrix cells. The reference cells contained in said array are accessed directly using a conventional DMA (Direct Memory Access) technique.
The features and advantages of a circuit structure according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.